The present disclosure relates generally to time to digital conversion and in particular to a sampling-based conversion.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A Time-to-Digital Converters (TDCs) is typically used to obtain a digital signal that represents a difference in time between two signals. TDCs are widely used for time interval measurements in space science, high-energy physics, laser range finders, and test instrumentation. Recently, TDC usage has been extensively applied to Phase Locked Loops (PLLs) and in particular to digital frequency synthesis using PLLs. In digital PLLs, the resolution of the TDC is an important performance metric which often limits the overall PLL performance. State-of-the-art TDCs are typically implemented based on the timing of gate delays or edge transitions. The resolution of such TDCs is thus limited by the gate delay.
FIG. 1 illustrates a conventional TDC 100, comprising a multistage delay line 102, flip-flops 104, and a counter 106. The time range that can be quantized by the TDC is a function of the number of stages (e.g., inverters) in the delay line 102. The quantization resolution is limited by the minimum gate delay (e.g., τ1) achievable with the particular process technology. For example, Complementary Metal Oxide Semiconductor (CMOS) processes may achieve a gate delay of about 10 pS.